DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 2399 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000
DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 2347 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000
DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 2541 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000
DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 3781 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK                                                    0x00060000L