DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 2380 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0
DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 2328 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0
DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 2522 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0
DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 3756 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT                                                 0x0