DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 4647 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0x0c000000L
DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 2525 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0xc000000