DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 4608 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x00000012
DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 2666 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x12