DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 4589 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x00003000L
DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 2659 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000