DCIO_HSYNCA_OUTPUT_SEL_PPLL1  123 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h 	DCIO_HSYNCA_OUTPUT_SEL_PPLL1                     = 0x1,
DCIO_HSYNCA_OUTPUT_SEL_PPLL1  892 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h 	DCIO_HSYNCA_OUTPUT_SEL_PPLL1                     = 0x1,
DCIO_HSYNCA_OUTPUT_SEL_PPLL1 1291 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h 	DCIO_HSYNCA_OUTPUT_SEL_PPLL1                     = 0x1,
DCIO_HSYNCA_OUTPUT_SEL_PPLL1 8112 drivers/gpu/drm/amd/include/navi10_enum.h DCIO_HSYNCA_OUTPUT_SEL_PPLL1             = 0x00000001,
DCIO_HSYNCA_OUTPUT_SEL_PPLL1 11644 drivers/gpu/drm/amd/include/vega10_enum.h DCIO_HSYNCA_OUTPUT_SEL_PPLL1             = 0x00000001,