DCIO_GSL_VSYNC_SEL_PIPE5  302 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h 	DCIO_GSL_VSYNC_SEL_PIPE5                         = 0x5,
DCIO_GSL_VSYNC_SEL_PIPE5 1071 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h 	DCIO_GSL_VSYNC_SEL_PIPE5                         = 0x5,
DCIO_GSL_VSYNC_SEL_PIPE5 1470 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h 	DCIO_GSL_VSYNC_SEL_PIPE5                         = 0x5,
DCIO_GSL_VSYNC_SEL_PIPE5 12008 drivers/gpu/drm/amd/include/vega10_enum.h DCIO_GSL_VSYNC_SEL_PIPE5                 = 0x00000005,