DCIO_GSL_VSYNC_SEL_PIPE3  300 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h 	DCIO_GSL_VSYNC_SEL_PIPE3                         = 0x3,
DCIO_GSL_VSYNC_SEL_PIPE3 1069 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h 	DCIO_GSL_VSYNC_SEL_PIPE3                         = 0x3,
DCIO_GSL_VSYNC_SEL_PIPE3 1468 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h 	DCIO_GSL_VSYNC_SEL_PIPE3                         = 0x3,
DCIO_GSL_VSYNC_SEL_PIPE3 12006 drivers/gpu/drm/amd/include/vega10_enum.h DCIO_GSL_VSYNC_SEL_PIPE3                 = 0x00000003,