DCIO_GSL_VSYNC_SEL_PIPE0  297 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h 	DCIO_GSL_VSYNC_SEL_PIPE0                         = 0x0,
DCIO_GSL_VSYNC_SEL_PIPE0 1066 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h 	DCIO_GSL_VSYNC_SEL_PIPE0                         = 0x0,
DCIO_GSL_VSYNC_SEL_PIPE0 1465 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h 	DCIO_GSL_VSYNC_SEL_PIPE0                         = 0x0,
DCIO_GSL_VSYNC_SEL_PIPE0 12003 drivers/gpu/drm/amd/include/vega10_enum.h DCIO_GSL_VSYNC_SEL_PIPE0                 = 0x00000000,