DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2  130 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h 	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2                  = 0x2,
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2  899 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h 	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2                  = 0x2,
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 1298 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h 	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2                  = 0x2,
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 8124 drivers/gpu/drm/amd/include/navi10_enum.h DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2          = 0x00000002,
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 11656 drivers/gpu/drm/amd/include/vega10_enum.h DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2          = 0x00000002,