DCIOCHIP_MASK_5BIT  525 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h typedef enum DCIOCHIP_MASK_5BIT {
DCIOCHIP_MASK_5BIT  528 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h } DCIOCHIP_MASK_5BIT;
DCIOCHIP_MASK_5BIT 1274 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h typedef enum DCIOCHIP_MASK_5BIT {
DCIOCHIP_MASK_5BIT 1277 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h } DCIOCHIP_MASK_5BIT;
DCIOCHIP_MASK_5BIT 1707 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h typedef enum DCIOCHIP_MASK_5BIT {
DCIOCHIP_MASK_5BIT 1710 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h } DCIOCHIP_MASK_5BIT;
DCIOCHIP_MASK_5BIT 8689 drivers/gpu/drm/amd/include/navi10_enum.h typedef enum DCIOCHIP_MASK_5BIT {
DCIOCHIP_MASK_5BIT 8692 drivers/gpu/drm/amd/include/navi10_enum.h } DCIOCHIP_MASK_5BIT;
DCIOCHIP_MASK_5BIT 9944 drivers/gpu/drm/amd/include/vega10_enum.h typedef enum DCIOCHIP_MASK_5BIT {
DCIOCHIP_MASK_5BIT 9947 drivers/gpu/drm/amd/include/vega10_enum.h } DCIOCHIP_MASK_5BIT;