DCIOCHIP_MASK_4BIT  517 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h typedef enum DCIOCHIP_MASK_4BIT {
DCIOCHIP_MASK_4BIT  520 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h } DCIOCHIP_MASK_4BIT;
DCIOCHIP_MASK_4BIT 1266 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h typedef enum DCIOCHIP_MASK_4BIT {
DCIOCHIP_MASK_4BIT 1269 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h } DCIOCHIP_MASK_4BIT;
DCIOCHIP_MASK_4BIT 1699 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h typedef enum DCIOCHIP_MASK_4BIT {
DCIOCHIP_MASK_4BIT 1702 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h } DCIOCHIP_MASK_4BIT;
DCIOCHIP_MASK_4BIT 8671 drivers/gpu/drm/amd/include/navi10_enum.h typedef enum DCIOCHIP_MASK_4BIT {
DCIOCHIP_MASK_4BIT 8674 drivers/gpu/drm/amd/include/navi10_enum.h } DCIOCHIP_MASK_4BIT;
DCIOCHIP_MASK_4BIT 9926 drivers/gpu/drm/amd/include/vega10_enum.h typedef enum DCIOCHIP_MASK_4BIT {
DCIOCHIP_MASK_4BIT 9929 drivers/gpu/drm/amd/include/vega10_enum.h } DCIOCHIP_MASK_4BIT;