DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK  505 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000
DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 14814 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000
DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 15448 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000