DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT  504 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 14813 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 15447 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10