DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK  487 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3
DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 14796 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3
DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 15430 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3