DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK  441 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000
DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 14754 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000
DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 15388 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000