DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK   77 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK 0x10000000
DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK 3380 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK                                                       0x10000000L