DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 1470 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 1378 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 1502 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 2469 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 1442 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 1889 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT  503 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT  385 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10