DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 1612 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 1560 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 1722 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 2791 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 1576 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 2143 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT  708 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT  581 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8