DB_RING_CONTROL__COUNTER_CONTROL_MASK 9568 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define DB_RING_CONTROL__COUNTER_CONTROL_MASK                                                                 0x00000003L
DB_RING_CONTROL__COUNTER_CONTROL_MASK 5220 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define DB_RING_CONTROL__COUNTER_CONTROL_MASK                                                                 0x00000003L
DB_RING_CONTROL__COUNTER_CONTROL_MASK 4694 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define DB_RING_CONTROL__COUNTER_CONTROL_MASK                                                                 0x00000003L
DB_RING_CONTROL__COUNTER_CONTROL_MASK 4527 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define DB_RING_CONTROL__COUNTER_CONTROL_MASK                                                                 0x00000003L
DB_RING_CONTROL__COUNTER_CONTROL_MASK 4113 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
DB_RING_CONTROL__COUNTER_CONTROL_MASK 4841 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
DB_RING_CONTROL__COUNTER_CONTROL_MASK 5371 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3