DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 9516 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT                                                                      0x10
DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 5194 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT                                                                      0xa
DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 4668 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT                                                                      0xa
DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 4501 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT                                                                      0xa
DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 3487 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x0000000a
DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 4074 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 4802 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 5332 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa