DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 9372 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK                                                           0x00100000L
DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 5082 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK                                                           0x00100000L
DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 4556 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK                                                           0x00100000L
DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 4385 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK                                                           0x00100000L
DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 3300 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00200000L
DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 3979 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 4705 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 5229 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000