DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 9271 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT                                                        0x4
DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 4993 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT                                                        0x4
DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 4467 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT                                                        0x4
DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 4292 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT                                                        0x4
DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 3281 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x00000004
DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 3912 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 4638 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 5162 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4