DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 21634 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT                                                                 0x8
DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 14342 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT                                                                 0x8
DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 15671 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT                                                                 0x8
DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 15533 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT                                                                 0x8
DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 3239 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x00000008
DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 3540 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 4264 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 4786 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8