DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 21647 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK                                                                   0x000F0000L
DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 14353 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK                                                                   0x000F0000L
DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 15682 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK                                                                   0x000F0000L
DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 15544 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK                                                                   0x000F0000L
DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 3230 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000f0000L
DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 3543 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 4267 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 4789 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000