CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR  469 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR  472 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h } CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR  466 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR  469 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h } CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR 2663 drivers/gpu/drm/amd/include/vega10_enum.h typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR 2666 drivers/gpu/drm/amd/include/vega10_enum.h } CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;