CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 6736 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT                                                                      0x10
CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 1258 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT                                                                      0x10
CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 1157 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT                                                                      0x10
CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 1124 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT                                                                      0x10
CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 2887 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x00000010
CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 3158 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 3772 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 4294 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10