CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 1223 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT                                                                  0x8
CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 1122 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT                                                                  0x8
CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 1089 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT                                                                  0x8
CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 2875 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x00000008
CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 3128 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 3742 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 4264 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8