CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 6702 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                          0x10
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 1218 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                          0x10
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 1117 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                          0x10
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 1084 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                          0x10
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 2847 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 3082 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 3696 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 4218 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10