CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 6704 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                            0xFFFF0000L
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 1220 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                            0xFFFF0000L
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 1119 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                            0xFFFF0000L
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 1086 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                            0xFFFF0000L
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 2846 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 3081 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 3695 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 4217 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000