CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 17595 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 10672 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 12175 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 11980 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 2717 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 1050 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 1368 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 1892 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16