CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 17594 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 10671 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 12174 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 11979 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 2715 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 1048 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 1366 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 1890 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14