CP_RB0_CNTL__CACHE_POLICY__SHIFT 17596 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_RB0_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
CP_RB0_CNTL__CACHE_POLICY__SHIFT 10673 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_RB0_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
CP_RB0_CNTL__CACHE_POLICY__SHIFT 12176 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_RB0_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
CP_RB0_CNTL__CACHE_POLICY__SHIFT 11981 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_RB0_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
CP_RB0_CNTL__CACHE_POLICY__SHIFT 2713 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x00000018
CP_RB0_CNTL__CACHE_POLICY__SHIFT 1052 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
CP_RB0_CNTL__CACHE_POLICY__SHIFT 1370 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
CP_RB0_CNTL__CACHE_POLICY__SHIFT 1894 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18