CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 18074 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT                                                         0x17
CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 11100 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT                                                         0x17
CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 12603 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT                                                         0x17
CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 12407 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT                                                         0x17
CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 2523 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x00000017
CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 1302 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 1660 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 2184 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17