CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 17968 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 11004 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 12507 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 12311 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 2405 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 1212 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 1546 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 2070 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b