CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 20189 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT                                                                  0x1e
CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 12879 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT                                                                  0x1e
CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 14205 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT                                                                  0x1e
CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 14070 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT                                                                  0x1e
CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 3360 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 3976 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 4498 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e