CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 20033 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT                                                                  0x10
CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 12733 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT                                                                  0x10
CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 14059 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT                                                                  0x10
CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 13924 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT                                                                  0x10
CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 3256 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 3876 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 4398 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10