CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 27238 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT                                                                0x12
CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 19422 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT                                                                0x12
CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 20755 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT                                                                0x12
CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 20682 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT                                                                0x12
CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 2163 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x00000012
CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 2620 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 3186 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 3708 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12