CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 6798 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT                                                            0x10
CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 1316 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT                                                            0x10
CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 1215 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT                                                            0x10
CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 1182 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT                                                            0x10
CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 2093 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x00000010
CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 3202 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 3816 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 4338 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10