CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 6797 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT                                                            0x0
CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 1315 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT                                                            0x0
CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 1214 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT                                                            0x0
CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 1181 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT                                                            0x0
CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 2091 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x00000000
CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 3200 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 3814 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 4336 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0