CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 6803 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT                                                         0x10
CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 1321 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT                                                         0x10
CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 1220 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT                                                         0x10
CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 1187 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT                                                         0x10
CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 2085 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x00000010
CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 3206 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 3820 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 4342 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10