CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 12597 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0
CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 12603 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0
CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 13219 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0
CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 56066 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 11495 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0
CORB_SIZE__CORB_SIZE_CAPABILITY_MASK  941 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 59131 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                                  0x00F0L