CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 20762 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 17694 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL