CLK_RESET_PLLC_BASE   34 arch/arm/mach-tegra/sleep-tegra20.S #define CLK_RESET_PLLC_BASE		0x80
CLK_RESET_PLLC_BASE   48 arch/arm/mach-tegra/sleep-tegra30.S #define CLK_RESET_PLLC_BASE		0x80