CLK_BASE__INST1_SEG1  310 drivers/gpu/drm/amd/include/arct_ip_offset.h #define CLK_BASE__INST1_SEG1                       0x00016E00
CLK_BASE__INST1_SEG1  191 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define CLK_BASE__INST1_SEG1                       0
CLK_BASE__INST1_SEG1  244 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define CLK_BASE__INST1_SEG1                       0x02401C00
CLK_BASE__INST1_SEG1  244 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define CLK_BASE__INST1_SEG1                       0x02401C00
CLK_BASE__INST1_SEG1  321 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define CLK_BASE__INST1_SEG1                       0
CLK_BASE__INST1_SEG1 1212 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define CLK_BASE__INST1_SEG1                      0
CLK_BASE__INST1_SEG1  218 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define CLK_BASE__INST1_SEG1                       0