CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT   29 drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004
CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT  112 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT  112 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT  112 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT  112 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT  112 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT  136 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5