CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT   27 drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000
CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT  148 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT  144 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT  144 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT  144 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT  144 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT  168 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0