BUS_CNTL__SET_MC_TC_MASK  340 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define BUS_CNTL__SET_MC_TC_MASK 0x0000e000L
BUS_CNTL__SET_MC_TC_MASK   55 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define BUS_CNTL__SET_MC_TC_MASK 0xe000
BUS_CNTL__SET_MC_TC_MASK   59 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h #define BUS_CNTL__SET_MC_TC_MASK 0xe000
BUS_CNTL__SET_MC_TC_MASK   57 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h #define BUS_CNTL__SET_MC_TC_MASK 0xe000
BUS_CNTL__SET_MC_TC_MASK 1516 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h #define BUS_CNTL__SET_MC_TC_MASK                                                                              0x0000E000L
BUS_CNTL__SET_MC_TC_MASK 17422 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define BUS_CNTL__SET_MC_TC_MASK                                                                              0x0000E000L
BUS_CNTL__SET_MC_TC_MASK 117697 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h #define BUS_CNTL__SET_MC_TC_MASK                                                                              0x0000E000L
BUS_CNTL__SET_MC_TC_MASK 20288 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h #define BUS_CNTL__SET_MC_TC_MASK                                                                              0x0000E000L