BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 56652 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                              0x7
BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 5456 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                              0x7
BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 7367 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                              0x7
BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 22477 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                              0x7