BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT 93650 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h #define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT                                                           0x8
BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT 24989 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT                                                           0x8
BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT 40024 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h #define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT                                                           0x8